1. Technical Field of the Invention
This disclosure relates generally to electronic circuits, and in particular to circuits for level translation.
2. Description of the Related Art
Level translation moves a signal from a first signaling voltage swing domain to a second domain. This translation is usually from a low-swing domain to a high-swing domain.
A common conventional solution for translating differential signals (usually at a lower voltage level) to complementary metal oxide silicon (CMOS) signals (usually at a higher voltage level) is to use a differential amplifier with a single ended output driving a trip-point skewed inverter.
FIG. 1 is a circuit diagram illustrating a conventional level translator circuit 100 that implements the conventional solution described above. The conventional level translator circuit 100 includes several circuit stages connected between a supply voltage VCC and a ground voltage VGND. The level translator circuit 100 includes two level shifters, an output stage, and a single ended output differential amplifier stage. Each stage has its own current source I1, I2, I3, I4 that sinks current into the ground node.
Differential inputs are applied at the inputs A_N and A_P of the level shifters. In one instance, the differential signal may be a USB 2.0 signal. The USB interface is described as version 2.0 “Universal Serial Bus Revision 2.0 specification,” which is available at the USB website ‘http://www.usb.org/developers/docs/’.
The output stage includes first and second inverters INV1 and INV2. A CMOS output OUT is obtained from the second inverter INV2.
The conventional level translator circuit 100 has several disadvantages. Although the level translator circuit 100 and other conventional circuits like it may be adjusted to work perfectly at any one process, voltage, and temperature (PVT), the duty cycle distortion (DCD) when measured across all conditions is terrible, in some cases approximately 35/65 (50/50 is the desired DCD). The output stage does not operate in its linear region, so the rise and fall times at the circuit node n1 varies significantly with process, voltage, and temperature (PVT). Thus, the trip point of the first inverter INV1 will vary widely with PVT. Also, the trip point of the first inverter INV1 is generally skewed upwards, which causes the rise time to become faster than the fail time. This variance increases over PVT compared to a balanced inverter.
The disparity described above distorts the CMOS output when compared to the differential input, and the narrowest input bit widths will have the output width reduced by the amount that the rise and fall delays differ. Consequently, the conventional level translator circuit 100 exhibits a widely varying delay disparity for 0-to-1 (low to high) and 1-to-0 (high to low) transitions across all operating conditions. For example, a 1.2 ns input width may be reduced to 1.0 ns at the output, which may not be acceptable for some implementations. It would be desirable to have a level translation circuit that had a much smaller delay disparity between high-to-low and low-to-high transitions.
Embodiments of the invention address these and other disadvantages of the conventional art.